Classical pulse width modulators (PWMs) difficulty a repetitive sequence of H contiguous logic highs (ones) adopted by L contiguous logic lows (zeroes). Every excessive and low lasts for a clock interval T = 1/F (Hz). The obligation cycle of the consequence might be outlined as H/N, the place N = H+L clock cycles. Usually N is an influence of two, however N might be any integer better than 0. A problem that have to be met with PWMs is to attenuate by filtering the dynamic AC portion of the stream whereas retaining its common DC worth. Over the complete vary of output sequences, the bottom frequency element F/N for classical PWMs can be the most important one, and subsequently probably the most tough to attenuate. Happily, there’s a easy trick which this Design Thought introduces that may ameliorate this problem.
Wow the engineering world along with your distinctive design: Design Concepts Submission Information
Earlier than discussing the trick, it’s value shortly reviewing different AC vitality mitigation strategies, all of which, just like the classical one, make use of counters of some kind as their driving engines. One strategy which I learn of years in the past however can not discover a reference to entails an M-bit psuedo-random sequence generator of N = 2M-1 states, every of whose bits is related to at least one enter of a numerical comparator [1]. The remaining enter is introduced with a quantity W. When the generator’s quantity is lower than W, the comparator outputs one; in any other case, it outputs zero. Because the generator is clocked, the result’s a random stream of W ones, N–W zeroes, and an obligation cycle of W/N. The spectral “white noise” nature of the result’s simpler to filter than the F/N-predominant element of a classical PWM.
An much more efficient mitigation is constructed into the {hardware} of some SAM D Microchip microcontrollers [2]. These PWMs modify 2X contiguous cycles of eight-bit classical PWM sequences to yield longer repeating sequences of size 2X+8. Right here X = 4, 5 or 6. For obligation cycles of Ok / 2X+8, 0 ≤ Ok < 2X+8, every eight-bit sequence has at the very least the integer portion of Ok/2X ones. The remaining Ok modulo 2X ones are unfold as evenly as doable among the many 2X eight-bit sequences. The result’s a protracted sequence of obligation cycle-modulated eight-bit sequences with little or no spectral vitality at and close to the bottom frequency F/2X+8 Hz generated, most of which is as an alternative at and close to F/28, and a much-simplified filtering drawback.
{Hardware} help for these approaches shouldn’t be at all times accessible. Happily, it’s available in most microcontrollers for the aforementioned trick whose description follows. As soon as the preliminary setup of an N = 2, 3 or 4…as much as 28 (and even 216) state counter driving a PWM is full, software-intervention-free “set it (the obligation cycle) and overlook it” PWM operation is inside straightforward attain. When the obligation cycle does should be modified, the specified worth of H is written to an output examine register (OCR). Usually, two PWMs with unbiased obligation cycles can be found, typically pushed by the identical counter. Take into account what might be achieved when benefit is taken of this mixture of capabilities.
In a single instance, the counters might be configured for N = 16. The PWMs can have obligation cycles of 1/16, 2/16, 3/16, all the way in which as much as 15/16. The remaining state might be both 0/16 or 16/16. The 2 PWM outputs are related by the collection mixture of two resistances in a ratio of 1:16. On the junction of those two resistors, there are 24×24 = 28 doable common values, simply as there can be with a single PWM presenting 28 completely different states. The only method to impact AC attenuation is to attach a capacitor between that junction and floor (Determine 1 is an instance of the whole circuit.)
Determine 1 An entire circuit representing the only technique to impact AC attenuation the place a capacitor is related between the junction of the 2 resistors on the PWM outputs and floor.
However each this and the normal PWM can profit from a extra complicated community with bigger numbers of resistors and capacitors, and optionally even an op amp to buffer the outcomes. The op amp can even allow the implementation of filters containing complicated pole pairs as an alternative of being restricted to actual poles, the actual poles being the one ones in any other case obtainable. The previous kind extra successfully minimizes the product of filter settling time and the magnitude of residual AC vitality. (An instance of such has been introduced in an earlier Design Thought.)
I used an ATmega16 microcontroller to implement the Determine 1 circuit. F was set to 1MHz, though a lot increased clock frequencies have been accessible. PWM 1 and PWM 2 have been configured to function in two completely different modes: as the 2 four-bit items described earlier than with outputs of unbiased values, and as eight-bit items with similar outputs. This maintained the identical R-C filter time fixed for each modes of operation. The repetitive sequences of the OCRs for every mode are listed in Desk 1.
Desk 1 OCR values utilized by the four-bit and eight-bit PWM modes for producing the Determine 2 waveform.
Determine 2 reveals a scope seize of one of many two modes; display screen photographs of the 2 modes are indistinguishable from each other, as are their roughly 18 mV resolutions. (It was needed to attach a further resistor, not proven, between the R1-R2-C1 junction and a adverse DC voltage. With out disturbing the R1-R2 ratio, this moved the waveform’s voltage near floor in order that the scope may show it with excessive decision.)
Determine 2 Waveform generated by programing the OCRs as listed in Desk 1 for each the four-bit and eight-bit PWM modes. The 2 modes’ outcomes seem similar for the reason that scope averages out AC vitality on the 200 ms/div sweep fee.
Every of the 2 four-bit PWMs has frequencies of F/16 = 62.5 kHz; the frequencies of the eight-bit ones are F/256 = 3.90625 kHz. The code modified the OCR registers roughly each 100 ms. On the Determine 2 sweep fee, the scope filtered out the PWM AC indicators, changing them with common values. At quicker sweep charges in subsequent figures, the scope revealed their peak-to-peak amplitudes. Determine 3 reveals 120 mV for the eight-bit PWMs, whereas Determine 4 reveals a mere 7.5mV for the four-bit ones.
Determine 3 The AC vitality throughout the capacitor within the Determine 1 circuit for the eight-bit PWM.
Determine 4 The AC vitality throughout the capacitor within the Determine 1 circuit for the four-bit PWM. The interval and amplitude are 16 instances smaller for the four-bit than for the eight-bit PWM.
With a step resolutions of 18 mV for each modes, the four-bit peak-peak noise is close to optimum at simply lower than half a step; any extra AC sign attenuation would needlessly improve the 1 ms half-step settling time. At 120 mV (6.7 steps) peak-to-peak at 1/16 the frequency, the eight-bit PWM implementation is just about unusable. The capacitor worth must be elevated to 15µF with an related 15x improve in settling time to fulfill the vitality attenuation efficiency of the twin four-bit PWM strategy.
The strategy employed on this instance is a strong one. With a pair of eight-bit PWMs interconnected with 0.1% resistors having a ratio of 256:1, a (twin eight-bit) 16-bit PWM can have an AC output that will be 256 instances simpler to filter than a classical 16-bit unit. PWM resolutions of lower than N = 216 or 28 ranges are additionally doable with concomitant reductions of PWM durations and related simplifications of filtering necessities. There are even microcontrollers with three or 4 PWMs whose outputs may be added along with an appropriate resistor community.
Christopher Paul has labored in numerous engineering positions within the communications trade for over 40 years.
Associated Content material
References
