The Cadence Joules RTL Design Studio permits front-end engineers to speed up and enhance register switch degree (RTL) design and implementation. By offering entry to the bodily data wanted for energy, efficiency, space, and congestion (PPAC) debugging, the software program permits customers to attain as much as 5 occasions quicker RTL convergence and as much as 25% improved high quality of outcomes.
Joules RTL Design Studio builds on the present Joules RTL Energy Answer by including visibility into RTL PPAC metrics. With its RTL debugging assistant, engineers can discover what-if eventualities and potential resolutions to attenuate iterations and enhance design outcomes. The software program shares the identical engines because the Innovus Implementation System, Genus Synthesis Answer, and Joules RTL Energy Answer, permitting entry to all evaluation and design exploration options from a single GUI.
Integration with the corporate’s generative AI Cerebrus Clever Chip Explorer lets customers discover design area eventualities, akin to floorplan optimization and frequency-versus-voltage tradeoffs. The Joint Enterprise Information and AI (JedAI) platform permits development and perception evaluation throughout totally different variations of the RTL design or throughout earlier mission generations.
For extra details about the Joules RTL Design Studio, in addition to associated merchandise, use the hyperlink to the product web page beneath.
Joules RTL Design Studio product web page
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