Minimizing passive PWM ripple filter output impedance

Simplicity and low price maintain the recognition of passive PWM DAC ripple filters regardless of their limitations. One among these limitations is a excessive output impedance attributable to the collection sum of filter resistance(s) (Rf in Determine 1, one resistor for every cascaded filter RC stage), making total DAC accuracy very delicate to output loading. The designers’ recourse, until they wish to resort to energetic output buffering and thus lose a few of that fantastic PWM simplicity and cheapness, is to make Rf as little as sensible. 

So, how low is sensible and what elements set the restrict?

Wow the engineering world together with your distinctive design: Design Concepts Submission Information

Determine 1 A generic passive PWM filter topology with one resistor (Rf) for every cascaded filter RC stage.

Though a ripple filter could comprise a number of phases, the primary stage will usually take heart stage within the “how low to go” determination, for these causes:

1. In just about all (even in multi-stage) ripple filter designs, Rf of later phases (if any) are proportional to the primary stage’s Rf. So, when it’s identified, they, and subsequently the ultimate DAC output impedance, are additionally identified.
2. To a very good approximation, the total peak-to-peak V+ PWM waveform amplitude often seems throughout the primary stage Rf, in order that practicality-limiting elements like energy and present draw are nearly totally decided by its resistance.  Worst case common energy and present draw usually happen at or close to 50% PWM obligation cycle and are given by:

Imax = V+ / (4Rf + 2Rn + 2Rp)
Pmax = V+² / (4Rf + 2Rn + 2Rp)

the place Rn is the N-channel swap’s on-resistance and Rp is the P-channel swap’s on-resistance.

Suppose we select 10 mW for optimum filter energy dissipation and V+ = 2.5V. Then filter output impedance is given by:

Z_10mW = Rf + (Rp + Rn)/2 = 2.5V² / 10 mW / 4 = 156 Ω

This 156 Ω can be a usefully low and loading-resistant output impedance (able to holding 8-bit accuracy towards 40k load resistance) and is definitely just like that of rail-to-rail buffer op amps when in zero-voltage output saturation. For comparability, contemplate a consultant RRIO op amp (the TLV237x) whose assured minimal output V when sinking 1 mA is 150 mV which converts to an equal impedance of:

0.15 V / 0.001 A = 150 Ω.

See Low-level output voltage on web page 8: https://www.ti.com/lit/ds/symlink/tlv2374-q1.pdf.

When Z =156 Ω, the ripple filter is sort of nearly as good as a buffered output in some circuit states. That is shocking efficiency for a easy and low-cost passive filter. However is it finally sensible? The arithmetic above implicitly assumes Rn = Rp. What occurs in the event that they’re not, as proven in Determine 2’s on resistance (Ron) versus supply or drain voltage (V) graph for the form of swap (TMUX4053) that is perhaps used to generate a precision 2.5 V PWM waveshape? 

Determine 2 On-resistance versus supply or drain voltage for the TMUX4053 with an unequal Rp and Rn at 25^oC.

At 25⁰C Rp is 77 Ω and Rn is 115 Ω. If we make:

Rf = 156 – (Rp + Rn) / 2 = 60 Ω

now the online resistance that prices the filter capacitor:

= Rf + Rp = 60 + 77 = 137 Ω

is considerably smaller than the resistance that discharges it:

= Rf + Rn = 60 + 115 = 175 Ω

by a symmetry issue of:                       

S = (Rf + Rp) / (Rf + Rn) = 137 / 175 = 0.78.

Sadly, whereas okay for minimizing output impedance, this a lot up/down resistance asymmetry is a nasty factor for DAC integral linearity. Determine 3 reveals the impact of S = 0.78 on linearity: A deal-breaking >6% of full-scale deviation from correct linearity.

Determine 3 Linearity error versus PWM obligation the place S = 0.78 creates ~6% of integral nonlinearity.

In actual fact, this can be a normal consequence. For any given S, integral nonlinearity of roughly:

INL ~ (1 – S) / 4

might be anticipated, with deviation from linear going optimistic for S<1 and destructive for S>1.

Due to this fact, if we wish abs(INL) = 2^-9 for trustworthy ½ lsb 8-bit linearity, we want:

abs(1 – S) = 4 * 2^-9 = 2^-7

and for the instance thought of:

(Rf + Rp) / (Rf + Rn) = 1 – 2^-7 = 0.9921875
Rf + Rp = 0.9921875 Rf + 0.9921875 Rn
(1 – 0.9921875) Rf = 0.9921875 Rn – Rp
Rf = 4749 Ω.

Thus, the output impedance should improve by 30-fold to 4.8 kΩ to revive 8-bit linearity, making minimal loading for 8-bit accuracy ~1.2M. Yikes!

However maybe there’s a easy and low-cost answer to even this badly bent linearity downside?

Truly, there may be. It consists of a simple arithmetic correction:

1. Let Vo = desired DAC output.

Then, as an alternative of setting PWM obligation to T = Vo / V+ per regular observe, substitute T* from

2. T* = T / (T + (1 – T) / S)

Then integral linearity shall be restored, offered that the worth offered for S is correct. Sadly, merely calculating S from typical Rn and Rp numbers taken from the swap datasheet will most likely not be correct sufficient. It could be preferable (possibly obligatory) to instantly measure S for the precise units used. However how are you going to measure Rn and Rp in an assembled circuit?

This simple in-circuit technique will work without having to hassle attempting to measure inside swap resistances:

1. Set PWM obligation issue = 0.5 = 50%
2. Learn Vo and V+ with a excessive impedance voltmeter.
3. Then S might be calculated as S = (1 – Vo/V+) / (Vo/V+).

Due to this fact, with this one-time voltage measurement and easy software-based correction, the minimal output impedance calculated above is appropriate with 8-bit DAC linearity and is finally sensible, in spite of everything. 

Ethical: Sure, you actually can go that low, no op amp required.

Stephen Woodward’s relationship with EDN’s DI column goes again fairly a good distance. Almost 100 submissions have been accepted since his first contribution again in 1974.

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