On two days in the middle of yearly, one in March heralding the beginning of spring and one other in September marking the primary of fall, the Earth’s axis of rotation aligns perpendicular to the rays of the Solar. Nowadays are the equinoxes and, because the title implies, divide daytime into nominally equal intervals of daylight and night time.
Wow the engineering world together with your distinctive design: Design Concepts Submission Information
Creator of a number of EDN design concepts, Jim McLucas (Mr. Equinox) evidently has a ardour and a expertise for devising circuits that additionally divide up time into equal intervals. He has printed a number of intelligent and revolutionary design concepts that convert arbitrary waveshapes into 50:50 sq. waves, thus slicing and dicing the time axis into equal segments. He’s additionally typically included a wide-range frequency doubler features:
I believed this regarded like a enjoyable idea and design problem, and Jim kindly gave me permission to borrow it and check out designing an “equinoctial” circuit of my very own. Determine 1 reveals the outcome.
Determine 1 Kibitzer’s model of a McLucas frequency multiplier and sq. wave generator.
Determine 1’s circuit includes two virtually an identical sections: enter processor, IP (U1pin1 by way of A1), and output generator, OG (U1p12 by way of A2).
The IP is able to working in both of two modes as chosen by jumper J1 or J2. J1 places the IP into 50:50 mode wherein it is going to settle for any obligation cycle enter and convert it to a symmetrical 50% obligation cycle sq. wave, appropriate for frequency doubling by the OG. (This circuit idea is only Mr. McLucas’s.) J2 places the IP into frequency-doubling mode wherein an enter waveshape that’s already 50:50 symmetrical is doubled earlier than enter to the OG for web frequency quadrupling.
When frequency doubling J2 is chosen, the mix of RC delays (R1C4 within the IP and R8C3 within the OG) and XOR gates (U1) generate excessive velocity pulses (~6 ns width) on every enter edge. Therefore two pulses per cycle and doubled frequency enter to the OG for quadrupled frequency. If J1 is jumpered as an alternative, then R1C4 is bypassed and only one pulse per cycle and an unmultiplied 50:50 sq. wave is generated by the IP for doubling by the OG.
The hearts of each IP and OG are easy however quick timing loops wherein a really quick monostable flip-flop is compelled by suggestions from an op-amp integrator to generate 50:50 sq. waves. (Yup. Jim’s concept once more.)
My variation on Jim’s fundamental timing loop idea consists of U3’s two D sort flip-flops and the encompassing elements, together with Schottky switching diodes D1 and D2, present sink transistors Q1 and Q2, and timing capacitors C1 and C2. As a result of the 2 loops are primarily an identical, let’s speak concerning the OG loop.
Every timing sequence begins when U1pin8 delivers a clock pulse to U3pin3. U3 is positive-edge-triggered and responds by driving U3pin6 low. This disconnects D2 from timing cap C2 and permits the present sink Q2 to ramp it down towards the switching threshold of U3pin 4 = -SET.
The timing interval thus begun has a length (~10 ns to 500 µs) decided by Q2’s collector present as managed in flip by integrator A2. The intent is to power the interval to be precisely 50% of the time between U1pin8 pulses. A2 does this by subtracting the two.5 V reference developed by the R6R7 voltage divider from the heartbeat practice at U2pin13 and accumulating the averaged distinction on suggestions capacitor C6.
If the obligation cycle at U2pin13 is <50%, indicating that the U3 timeout is simply too lengthy, A2’s output will ramp up, growing Q2’s collector present and C2 ramp charge, thereby making the timeout shorter. If it’s >50%, A2 will ramp down, lowering IcQ2 and lengthing the timeout. Web outcome: after a number of seconds, U2pin13 will output an precisely 50:50 sq. wave at 2 or 4 occasions (relying on J1 J2) the enter frequency.
Offered, in fact, that mentioned frequency is throughout the limits of the timing loop.
The excessive finish of mentioned frequency vary is principally restricted by the propagation delays of U3, Q2 ,and D2. These sum to about 10 ns (possibly a smidgeon much less) and thus restrict the max frequency to ~1/(10 ns + 10 ns) = ~1/20 ns = ~50 MHz (or presumably a bit extra). The low finish is proscribed by leakage currents (primarily by way of D2) that may trigger C2 to proceed to ramp down even when A2 turns Q2 fully off. This leakage can sum to upwards of 10 nA (particularly if the diode is heat) and units a bottom-end interval of ~1 ms and a temperature-dependent minimal frequency of (very) roughly ~1/(1 ms + 1 ms) = ~1/2 ms = ~500 Hz.
OG output is routed by way of U2pins 6 and eight and summed by R12 and R13 to supply a handy 5 Vpp, ~50 Ω output. If no enter is offered, the output shuts down at zero volts, stopping overheating of U2.
An extra element is A3. It serves as an IP obligation cycle comparator that holds OG timing loop exercise disabled till the IP has converged (or almost so) on and is producing an correct 50:50 pulse practice. This avoids the opportunity of the erratic and protracted confusion of the OG suggestions loop, which might happen if it’s allowed to attempt to converge prematurely.
It was certainly a enjoyable mission—all issues being “equal”. Thanks, Jim!
Stephen Woodward’s relationship with EDN’s DI column goes again fairly a good distance. Practically 100 submissions have been accepted since his first contribution again in 1974.
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