Maker Evan Allen has constructed a instrument for debugging traditional 74- and 40-series transistor-transistor logic (TTL) chips with out having to take away them from a circuit — by hooking them as much as a field-programmable gate array (FPGA) and evaluating their responses to a Verilog simulation of the identical half.
“This undertaking is meant to permit for the in-circuit testing of 74xx and 40xx type logic chips,” Allen explains of the trouble, dropped at our consideration by Adafruit. “We try this by sampling all of the pins of a given chip (inputs and outputs) and examine the habits of the true chip to at least one that we mannequin in Verilog. This lets the circuit function usually, wiggling the enter pins and we are able to observe these modifications and examine them to the chip’s output pins.”
A 64-pin 5V add-on for the Mojo V3 FPGA improvement board turns it right into a TTL-testing powerhouse. (📷: Evan Allen)
The {hardware} is a mixture of an AMD Xilinx Spartan 6 FPGA on a Mojo V3 improvement board and an add-on protect which gives 64 pins of bidirectional 5V-tolerant enter/output (IO) — permitting it to soundly talk with the 5V TTL logic chips that are the goal of a take a look at. As soon as wired into the circuit internet hosting the chip to be examined, the FPGA analyses the responses it receives and compares them to a super simulation of the identical half written within the Verilog {hardware} description language (HDL).
“The output from this mannequin is a sign that represents a discrepancy between the mannequin and the precise chip,” Allen explains. “Within the case of an excellent chip that represents the propagation delay, for a foul chip that may differ from the proper sign for fairly some extra time than a number of clock cycles. That distinction sign is fed into the counter perform that counts up and if any one of many channels is constantly off by various clock cycles in a row it latches a flag output. These flags are wired to the LEDs on the Mojo board. The debug pins are assigned to the distinction alerts so we are able to see precisely how a lot the sign from our actual chip differs from the mannequin.”
The FPGA checks the chip compared to a simulated superb, written in Verilog. (📷: Evan Allen)
The comparability can spotlight when there’s an issue — however, Allen admits, it may’t at all times observe down precisely the place. “We will get an thought of whether or not a chip is dangerous,” he explains, “however the chip beneath take a look at just isn’t essentially inflicting the difficulty, it’s attainable that one thing on the identical internet because the output pin is interfering with the sign. Hopefully I’ll be capable to construct up a collection of fashions and clip proper on to a operating system to get an thought of whether or not there’s any motive to desolder and test a given chip out of circuit.”
Allen’s full write-up is offered on his weblog, with supply code printed to GitHub beneath the permissive MIT license. The bidirectional 5V protect for the Mojo V3 improvement board, in the meantime, is offered on PCBWay.
