The 8-bit decision of a peripheral DAC (such because the ATtiny household, as an example) is usually inadequate. Let’s see how the issue might be solved utilizing on-chip assets.
The circuit in Determine 1 reveals a way to enhance the decision of a peripheral DAC. The circuit additionally reduces output resistance of the DAC and might scale back its offset (which is moderately pronounced for ATtinyx17).
Determine 1: Circuit used to enhance the decision of a peripheral DAC whereas additionally decreasing the output resistance and offset of the DAC.
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This straightforward strategy is absolutely static (wants no extra capacitors with their imperfections and cost refreshing), it preserves the monotonicity of the unique DAC, however might require some tuning to attain one of the best linearity.
So as to add yet one more bit you should use any free port of your MPU, in Determine 1, this port is marked as Pxn (x=A … C, n=0 … 7). (And sure, you possibly can add a couple of bit this fashion.)
Notice: The port Pxn ought to be configured as an output earlier than utilizing it as an additional bit for the DAC. Additionally keep in mind these very helpful directions in AVR ASM, which might selectively change one bit in a row.
The little bit of the Pxn can be utilized as a brand new most vital bit (MSb), or a brand new least vital bit (LSb)—an in depth description of the final case is given beneath.
To take care of the integrity of the output, each the DAC0 and the Pxn ought to have the identical headroom on their outputs. The best option to safe that is to decide on +VDD as VREF for the DAC. In fact, the worth of +VDD must be well-regulated on this case.
The op amp ought to present ample velocity and precision the place the entire added error on the output of the op amp is:
Er = Vos * (1 + R5 / Req),
the place Vos is the offset voltage of op amp and Req = R1||R3 (roughly).
The worth of Er ought to be a minimum of lower than 1 LSb of the modified DAC.
The minimal voltage on DAC0 OUT is about 0.2 V (for ATtinyx17). If this offset is okay to your utility, you possibly can exclude resistors R3 and R4, and use just one +E provide, however, the op amp ought to have: a rail-to-rail output, a ample precision, and be capable to work with close to zero enter.
To scale back the minimal worth of e0 to zero, it’s essential to zero the output with the resistors R3 and R4 whereas DAC0 will get its zero code.
The values of all resistors might be calculated as follows:
R1 ≥ 5.6k (the requirement from the datasheet of ATtinyx17).
Let N bits be the unique DAC decision. Then:
R2 = R1 * 2^(N+1) (some last tuning might present the higher consequence).
For the reason that minimal voltage on DAC0 OUT is about 0.2 V,
R3 + (R4/2) = 5*R1 / 0.2 (If VDD = E = 5 V)
R3 = 0.8*(5*R1 / 0.2)
R4 = R3 / 2 (R4 is a multi-turn pot).
The resistor R5 can simply conform the DAC output to the values anticipated by an utility.
Some efforts could also be required in this system code to synchronize the DAC0 OUT and Pxn, albeit there are purposes which might tolerate the de-synchronization if it isn’t very giant (lower than tens of microseconds).
Notice: the output of the op amp is inverted in comparison with the DAC0 OUT (therefore the signal “-” earlier than e0 in Determine 1). You may address this by including an inverter (op amp) to the output, or by making a change within the code, which can be a greater resolution.
You shouldn’t anticipate that the earlier maximal worth of the conversion charge could be left unchanged. Each subsequent added bit means a resistance that’s twice as giant in addition to some added capacitance within the summing node.
So, the settling time can be unavoidably bigger with each enlargement bit added.
To scale back a parasitic capacitance within the inverting node of the op amp the resistors R1, R2, R3, and R5 ought to be positioned near the inverting enter.
Generally to optimize the efficiency of the DAC (to compensate the amplifier), the capacitor C3 (10-40 pF) must be linked in parallel with R5.
—Peter Demchenko studied math on the College of Vilnius and has labored in software program improvement.
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