Packing 18.5 million system logic cells, AMD’s Versal Premium VP1902 adaptive SoC aids the verification of more and more advanced ASIC and SoC designs. The chiplet-based machine is optimized for emulation and prototyping, doubling the programmable logic density and mixture I/O bandwidth of the previous-generation Virtex UltraScale+ VU19P FPGA.
As complexity grows in ASIC and SoC designs, particularly with the fast development of AI and ML-based chips, in depth verification of each silicon and software program earlier than tape-out is required. In accordance with AMD, FPGA-based emulation and prototyping offers the best degree of efficiency, permitting sooner silicon verification and enabling builders to shift left within the design cycle and start software program growth nicely earlier than silicon tape-out.
Along with elevated logic density and mixture I/O bandwidth, the VP1902 adaptive SoC leverages the Versal structure. This contains Versal’s programmable network-on-chip, enabling the VP1902 to ship as much as 8 instances sooner debugging in comparison with the VU19P. It is usually supported by AMD’s Vivado ML design suite, which incorporates automated design closure help, interactive design tuning, distant multi-user real-time debugging, and enhanced back-end compilation.
The AMD Versal Premium VP1902 adaptive SoC will start sampling in Q3 2023 to early entry clients, with manufacturing anticipated within the first half of 2024.
Versal Premium VP1902 product web page
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