When somebody notices that two 8-bit DACs might be purchased for lower than one 16-bit DAC, a basic query is usually requested: Why can’t you merely take two 8-bit DACs, assign one to the MSByte, the opposite to the LSByte, sum their outputs in a 28:1 ratio, and get 16 bit decision (or close to) for affordable? The likewise basic (however disappointing) reply is: Effectively, you’ll be able to strive, however you in all probability gained’t just like the end result. This prediction is often true primarily due to two elements: #1, poor differential nonlinearity (DNL), and #2, mismatch between typical 8-bit DACs.
The DNL of basic “resistor ladder” structure DACs, typified in Determine 1, is seldom a lot better than the ~1/2 lsb that’s ok to ensure monotonicity, however solely simply.
Determine 1 The DNL typical of basic “resistor-ladder” DACs.
Consequently, when two such “basic” DACs are mixed, little or no enchancment in helpful decision can occur. Fortuitously, there’s another. The inherent DNL of a “resistor string” kind DAC is a lot better, as illustrated in Determine 2.
Determine 2 The DNL typical of “string” kind DACs (e.g., TLV5624).
So, supplied the suitable DAC structure is chosen, is there hope in spite of everything for our money-saving plan?
Sadly, #2, the mismatch downside, stays unsolved. Two 8-bit DACs simply can’t be anticipated to have output scale elements that match and sum to a end result that’s considerably extra correct than required for 8-bit precision—clearly insufficient for our prolonged decision software. Nevertheless, what if each bytes of the 16-bit enter might be transformed by the identical DAC? One DAC can fairly be anticipated to precisely match itself!
A current design concept (DI) suggests how this could be carried out (i.e., get one DAC to do double responsibility). Within the earlier DI, the Shannon Decoder idea (see Determine 3), is defined. It employs (what’s successfully) a 1-bit DAC to do multi-bit digital to analog conversion by the dynamic summation of successive conversions in a easy T/ln(2) RC time fixed.
Determine 3 The Shannon decoder dynamic DAC.
The trick that could be helpful right here is that this: the Shannon Decoder precept isn’t restricted to working with a 1-bit DAC. If as an alternative of a time fixed of RC = T/ln(21) the fixed is made to be T/ln(28), then an 8-bit DAC might be accommodated. That is carried out in Determine 4.
Determine 4 The Shannon decoder precept utilized to extending 8-bit DAC decision.
U1 is an 8-bit, voltage output, resistor-string kind DAC (e.g., TLV5624) managed by a typical SPI serial interface, plus a separate output bit (CNV = Convert/-Maintain).Â
Every conversion cycle is 2Tby = 40 µs lengthy (for a 25kHz replace fee) as illustrated in Determine 5.
Determine 5 The Shannon conversion sequence.
Because the cycle begins with loading the Lsby of a 16-bit conversion worth. Simultaneous assertion of Body Sync (FS) and Convert (CNV) outputs the Lsby worth and switches U2 in order that R1 is related to C1, making a Shannon summation time fixed of
R1C1 = Tby/ln(28) = 3.610 µs.
 Consequently, after the 20 µs Tby interval, the cost on C1 is
 Vc1 = (256/28)Lsby = Lsby.
Whereas that’s taking place, the Msby is loaded over the SPI interface in order that when the second FS pulse happens the Msby worth is output, starting its accumulation by the R1C1 time fixed, whereas the beforehand amassed Lsby de-accumulates.Â
After the second Tby = 20 µs interval,
Vc1 = (256/28)Msby + (256/216)Lsby = Msby + Lsby/28,
 which is the ultimate 16-bit end result, and the conversion cycle is full.
CNV now returns low, inflicting Vc1 to be sampled and transferred to C2 by unity-gain follower U3, the place it’s held till up to date by subsequent conversion cycles.
Stephen Woodward’s relationship with EDN’s DI column goes again fairly a methods. In all, a complete of 64 submissions have been accepted since his first contribution was revealed in 1974.
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