ANSYS is leveraging its 3D-IC design expertise simulation software program to remodel chip integration by enhancing efficiency, lowering energy consumption, and shrinking kind components for next-generation units. Marc Swinnen, Director of Product Advertising, discusses the affect of thermal administration on stacking density in multi-die techniques with EFY. Learn on…
Q. What’s Ansys RHSC ET, and what does it supply concerning semiconductor chip-package-system design?
A. Ansys RedHawk-SC Electrothermal (RHSC ET) is a verification product designed to analyse 2.5D/3D-IC multi-die semiconductor configurations. These techniques sometimes contain chiplets and HBMs on an interposer or substrate inside a bundle enclosure. It conducts thermal, energy, sign, and structural integrity analyses on the system.
It might probably collaborate with different Digital Design Automation (EDA) instruments to analyse chips at completely different scales, from nanometres to millimetres to meters, guaranteeing complete system understanding. RHSC ET facilitates multi-scale evaluation throughout varied physics domains, from prototyping to manufacturing signoff. It manages a set of Decreased Order Fashions (ROMs) out there within the Ansys platform, together with chip energy, thermal, sign, and electrostatic discharge fashions. RHSC ET performs meeting and full-system evaluation utilizing these fashions, incorporating components like heatsinks and fluid dynamics simulations.
Q. What are the important thing business developments and rising challenges in thermal simulation for 3D-IC designs?
A. Whereas most multi-die designs at this time are carried out as 2.5D designs, there’s a clear want for the upper integration densities achievable with 3D stacking expertise. The first impediment to this growth is thermal administration. Cooling 3D assemblies is inherently more difficult. Progressive methods, resembling devoted thermal-spreader layers within the metallic stack, are being developed, together with superior cooling strategies, together with liquid cooling.
That is accompanied by a corresponding emphasis on lowering warmth manufacturing. Low energy design is now a major concern, even for merchandise not reliant on battery energy.
3D-IC design has elevated thermal evaluation to a top-level design parameter throughout prototyping, reasonably than solely on the packaging stage, to stop overheating points. When planning a multi-die structure, understanding which chiplets generate warmth and after they accomplish that is essential. Inserting two chiplets subsequent to one another that occur to warmth up concurrently can jeopardise the complete design.
Q. How does the RHSC ET software program account for the stacking of a number of layers and their affect on thermal administration?
A. Thermal administration is the basic constraint on most integration density or how small a system will be. A single high-performance chip can simply eat 100W to 200W. Cooling can not exceed a sure energy density restrict, leading to thermal runaway, parameter drift, mechanical warping, or melting when stacking a number of parts close to or on prime of one another.
The Ansys platform presents instruments that simulate the three core features of thermal administration: energy/warmth era, warmth conduction, and warmth dissipation.
Warmth is generated in silicon chips primarily based on their exercise and energy provide currents, captured by our chip thermal fashions (CTMs). The software program fashions warmth conduction and distribution all through a 3D-IC setup utilizing CTMs for every chip, interposer, and bundle. Ansys meshing and thermal conduction simulators illustrate warmth stream over time. The ultimate temperature depends on efficient warmth dissipation by means of system-level parts resembling warmth sinks, thermal spreaders, and cooling followers. This technique-level simulation additionally employs different software program to mannequin heat-sink and air stream utilizing computational fluid dynamics (CFD) simulation.
Q. How user-friendly is the software program for engineers and designers who usually are not specialists in thermal evaluation?
A. Thermal evaluation is well-established for Ansys however comparatively new for many 2.5D/3D-IC silicon designers. Traditionally, thermal issues had been typically addressed later within the bundle design course of, however they’re now integral from the prototyping section. Many firms wrestle to coordinate experience throughout varied groups – chip, bundle, and system PCB. These groups encounter difficulties in aligning their efforts because of the interconnected nature of 3D-IC design.
The aim of Digital Design Automation (EDA) instruments is to simplify expertise functions. Our software program streamlines the appliance of Ansys’s simulation and meshing engines to 3D-ICs, particularly for brand spanking new customers. Given the evolving 3D expertise panorama and the absence of normal workflows, flexibility is important to accommodate various buyer approaches.
Q. Please share insights into thermal simulation software program adoption charges for 3D-IC designs throughout completely different industries.
A. The first adopters of multi-die design embody:
- Excessive-capacity reminiscence producers: The overwhelming majority now make use of multi-die stacks often known as ‘excessive bandwidth reminiscence’ (HBM).
- Excessive-performance computing (HPC) market: Most high-end microprocessors, cellular utility processors, and graphic processors are designed as 2.5D implementations.
- Picture sensor producers: CMOS picture sensors (CIS) in most digital digital camera techniques are exploring 3D stacking of the sensor with picture processing logic.
Q. What insights does the software program present for optimising energy supply and lowering power-related points?
A. From real-world software program affect to ambient warmth dynamics, RHSC ET charts a course in the direction of effectivity and reliability in 3D-IC design.
- Actual-World Software program Affect: RHSC ET accounts for the thermal results of operating precise software program functions on the 3D-IC stack, utilizing exercise units from actual software program apps, typically obtained from {hardware} emulators. This method is important for dependable thermal evaluation.
- Mechanical Warpage and Stresses: The instrument simulates mechanical warpage and stresses within the multi-die stack brought on by differential thermal enlargement. These stresses can affect system reliability and lifespan, probably resulting in microbump cracking and purposeful errors as a consequence of adjustments in transistor parameters.
- Materials Affect on Thermal Conduction: The thermal conduction in a part stack is influenced by materials properties. Our software program interfaces with a supplies database system, permitting designers to experiment with completely different supplies to seek out the optimum mixture contemplating thermal and electrical properties.
- Ambient Warmth Affect: The instrument additionally considers the affect of ambient warmth on system efficiency. For example, ambient temperature variations can have an effect on the digital meeting if the 3D-IC meeting is positioned close to a automobile engine with fluctuating temperatures.
These capabilities are invaluable for correct and complete thermal evaluation.
Q. What do you imply by electromigration reliability? How does RHSC ET expertise assess and predict electromigration reliability in 3D-IC designs?
A. Electromigration is a bodily impact the place a powerful electrical present bodily strikes metallic atoms in a wire, akin to a powerful river present transferring rocks downstream. This metallic migration leads to ‘voids’ (lacking metallic that has migrated away) and ‘hillocks’ (accumulations of metallic which have moved upstream) in chip interconnects. Electromigration is a comparatively sluggish course of that may take months and even years to manifest as an issue. Subsequently, it can’t be detected by testing throughout the manufacturing stage, however reasonably by means of correct design practices.
The silicon foundries (manufacturing crops) specify a most allowable present for a given wire cross-section that can not be exceeded. RedHawk-SC and Totem can confirm the present by means of each one of many billions of polygons that make up a chip’s interconnect, flagging any violations earlier than manufacturing. Fixing electromigration points entails widening wires, lowering present, or each.
Electromigration is a priority wherever giant currents cross by means of very skinny wires. That is primarily an on-chip subject, however fashionable 2.5D/3D-IC interconnects, particularly on silicon interposers connecting a number of dies, have grow to be so skinny that it is usually a priority for 3D-IC assemblies.
Q. How does the software program handle coupling impact challenges in 2.5D and 3D IC techniques?
A. The market presents quite a few multi-die applied sciences from all main foundries. 3D-IC strictly refers to vertically stacked dies, whereas 2.5D refers to side-by-side die placement on an interposer. Though most designs at this time are technically 2.5D assemblies, they sometimes embody 3D HBM (excessive bandwidth reminiscence) stacks. To simplify issues, “3D-IC” is usually used as an umbrella time period for all these applied sciences.
RHSC ET handles each 2.5D and 3D expertise choices adeptly. Thermal results are extra pronounced in 3D stacking than in 2.5D, however the identical software program is used to analyse each.
Q. How does the software program handle the computational calls for of large-scale multiphysics simulations for two.5D/3D-IC techniques?
A. A single die in a 2.5D/3D-IC system incorporates billions of transistors, and multi-die setups include a number of dies, interposer layers, through-silicon-vias (TSVs), and microbump connections. Two approaches deal with this information complexity in multi-die techniques:
In depth use of cloud computing – Our cloud-optimised elastic compute information infrastructure, SeaScape, allows detailed evaluation of full chips.
Hierarchical modelling with Decreased Order Fashions (ROMs) – These fashions seize key bodily results precisely, enabling complete system-level evaluation whereas minimising information necessities. ROMs cowl chip energy, thermal, sign, electrostatic discharge fashions, interposer and bundle behaviour. They’re utilized in system-level evaluation on the board degree as properly.
Q. How does the software program deal with modelling heterogeneous techniques with a number of dies, interposers, packages, and PCBs? What degree of element can it obtain?
A. The advisable method for complete heterogeneous full-system evaluation utilizing RHSC ET is hierarchical modelling with Decreased Order Fashions (ROMs). These fashions present enough element for system-level evaluation whereas minimising information necessities. ROMs embody main bodily results, resembling chip energy, thermal, sign, and electrostatic discharge fashions.
Every ROM is generated from an in depth signoff evaluation of particular person parts like chiplets, interposers, and packages, utilizing applicable instruments resembling RedHawk-SC, Totem, and RaptorX.
RHSC ET combines ROMs to analyse the complete 2.5D/3D stack. It might probably even use a mixture of ROMs and full-data fashions to attain accuracy versus runtime trade-offs. Icepak employs ROMs to compute PCB-level thermal situations (heatsinks, followers), whereas SIwave makes use of them for PCB-level EM/IR evaluation.
Q. What challenges does the mannequin encounter in creating correct bodily fashions and verifying their connectivity?
A. The problem in creating ROMs lies in balancing inside visibility with information measurement. For optimisation functions, designers might wish to establish inside ROM particulars linked to top-level system points. That is attainable however reduces the information discount achieved by the ROM.
Relating to connectivity, RHSC ET is a multiphysics evaluation platform that integrates with widespread bodily design instruments (e.g., 3DIC Compiler from Synopsys). These design instruments primarily guarantee appropriate connectivity by means of the multi-die stack.
