Shannon decoder DAC meets UART

If you want to rapidly and inexpensively convert a binary quantity right into a proportional analog voltage, one cool (and simply isolated) strategy to do it’s:

  1. Serialize the quantity right into a bit stream with the LSB output first,
  2. enter the ensuing stream into an RC time fixed with
  3. RC = T/ln(2) the place T = the inter-bit interval, and
  4. seize the ultimate built-in voltage on the finish of bit string enter with a S&H.

Wow the engineering world together with your distinctive design: Design Concepts Submission Information

This methodology is conceptualized because the Shannon decoder DAC (SDD) in Determine 1.

Determine 1: The Shannon decoder DAC (SDD) idea.

Making use of the SDD idea to implementation of a DAC (or a number of DACs) advantages from some helpful information.

  1. Serializing and outputting binary numbers with LSB first is precisely what the usual common asynchronous receiver/transmitter perform (UART) does, and
  2. UARTs are extensively and inexpensively obtainable, each as USB-driven exterior RS232 peripherals for PCs (usually utilizing the favored FDTI or comparable chipsets and obtainable absolutely cabled and connectorized for lower than $10) and as inner peripherals in standard microcontroller chips (the TM4C123x incorporates eight!).

Determine 2 illustrates an SDD for 5-volt asynchronous serial information of the type a µC UART would possibly output, and Determine 3 is its timing diagram. Right here’s the way it works.

Determine 2 The SDD with 5V asynchronous serial information, much like a µC UART output.

Determine 3 The SDD conversion cycle timing for 5V logic ranges.

Serial transmission of bytes (at T = 8.68 µs = 115200 baud) for DA conversion follows normal UART formatting and begins with a ‘0’ begin bit. This triggers the U2 555 timer through U1a and begins a (R2 + R3)C3 ln(3) = 78.1µs = 9T conversion cycle, driving U1b to isolate the C2 maintain capacitor (which holds the earlier conversion end result) and join the C1 pattern capacitor to the R1 enter integration resistor. Discover that

R1C1 = (R1 + Ron(U1c + U1b))C1 = (12400 + 140).001 µF = 12.54 µs = 8.69 µs/ln(2) is actually similar to the theoretical Shannon time fixed of T/ln(2), and differs from the best by solely 0.13%, assuming nominal part values.

The U1c swap converts logic ranges to U4’s reference ranges and applies the ensuing precision 0/+5.0V bitstream to R1C1. The conversion course of continues for

8T = 69.4 µs. U2 then occasions out, driving CNV low, inflicting U1b to switch the amassed conversion end result cost on C1 to C2 and from there to U3’s voltage follower unity-gain output.

U2 then resets, arming the circuit to reply to the subsequent information enter cycle when the subsequent begin bit arrives, finishing the 10T = 86.8 µs = 1/11.52 kHz ripple-free conversion cycle. Increased baud charges and even sooner conversion occasions are additionally simply attainable.

Bipolar RS232 signaling, with its superior noise immunity, may also be simply accommodated by a special configuration of the U1a and U1c interface switches, as proven in Determine 4.

Determine 4: The SDD enter modified for RS232 sign ranges and polarity.

Determine 5 exhibits the ensuing revised conversion timing.

Determine 5: The SDD analog conversion from RS232 sign ranges.

Stephen Woodward’s relationship with EDN’s DI column goes again fairly a good distance. In all, a complete of 64 submissions have been accepted since his first contribution was revealed in 1974.

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