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Intel co-founder Gordon Moore famously predicted that the variety of transistors on a chip would double each one to 2 years. Often called Moore’s Regulation, this forecast held true till just lately due to developments in pattern-miniaturization expertise. Nonetheless, Moore’s Regulation could not be legitimate as technological developments have reached their limits and prices have risen from using costly gear reminiscent of excessive ultraviolet (EUV) lithography programs. In the meantime, there’s nonetheless nice market demand for ever-improving semiconductor applied sciences. To bridge this hole in technological development and meet the semiconductor market’s wants, one resolution has emerged: superior semiconductor packaging expertise.
Though superior packaging is extremely advanced and entails a large combination of applied sciences, interconnection expertise stays at its core. This text will cowl how packaging expertise has developed and SK hynix’s latest efforts and accomplishments in serving to to advance the sector.
The significance of interconnection in superior packaging
First, it is very important be aware that interconnection expertise is a crucial and crucial a part of packaging. Chips are interconnected by way of packaging to obtain energy, trade indicators, and, in the end, function. Because the pace, density, and capabilities of a semiconductor product change relying on how the interconnection is made, interconnection strategies are consistently altering and growing.
Along with growing numerous processes to comprehend high-quality patterns in fabs, there have been complete efforts to advance interconnection methods within the packaging course of. Consequently, the next 4 sorts of interconnection methods have been developed: wire bonding, flip-chip bonding, through-silicon through1 (TSV) bonding, and hybrid bonding with chiplets.2
1By-silicon through (TSV): A sort of vertical interconnect entry (through) that utterly passes by way of a silicon die or wafer to allow the stacking of silicon cube.
2Chiplet: Know-how that divides chips by use reminiscent of controller or high-speed reminiscence and manufactures them as separate wafers earlier than re-connecting them within the packaging course of.
3Hybrid bonding has not been utilized to the above merchandise. Specs are an estimate.
Wire bonding
Wire bonding is the primary interconnection technique that was developed. Sometimes, supplies with good electrical properties reminiscent of gold, silver, and copper are used as wires to bond chips and substrates. That is essentially the most cost-effective and dependable interconnection technique, however on account of its lengthy electrical path, it’s not appropriate for newer units that require high-speed operations. Consequently, this technique is being adopted for cell DRAM and NAND chips utilized in cell units that don’t require fast operations.
Flip-chip bonding
Flip-chip bonding overcomes the shortcomings of wire bonding. The size of its electrical path is a number of tenths of that present in wire bonding, making it appropriate for high-speed operations. Processed on the wafer degree, flip-chip bonding additionally affords superior productiveness in comparison with wire bonding that’s carried out on the chip degree. Consequently, it’s extensively used within the packaging of CPUs, GPUs, and high-speed DRAM chips. Furthermore, as bumps could be fashioned on your complete aspect of the chip, it’s potential to have extra inputs and outputs (I/O) than wire bonding — doubtlessly offering larger data-processing speeds. Nonetheless, flip-chip bonding has its personal disadvantages. First, it’s troublesome to carry out multi-chip stacking, which is detrimental for reminiscence merchandise that require excessive density. As well as, though flip-chip bonding can join extra I/Os than wire bonding, its bump pitch3 and natural PCB pitch forestall the connection of an excellent larger variety of I/Os. To beat these limitations, TSV bonding was developed.
By-silicon through (TSV) bonding
As an alternative of utilizing the standard technique of wiring to attach chip-to-chip, TSV connects chips vertically by drilling holes within the chip and filling them with conductive supplies reminiscent of steel to accommodate electrodes. After the wafer with TSV is fabricated, microbumps are fashioned on its prime and backside sides by way of packaging earlier than these bumps are related. As TSV permits the bumps to be related vertically, it allows multi-chip stacks. Initially, stacks utilizing TSV bonding had 4 layers earlier than this was elevated to eight. Extra just lately, a method made it potential to stack 12 layers, and in April 2023 SK hynix developed its 12-layer HBM3. Whereas the tactic for flip-chip bonding with TSV sometimes makes use of thermocompression-based non-conductive movie (TC-NCF), SK hynix makes use of the MR-MUF4 course of, which may scale back the stress from stacking and allow self-alignment.5 These options made it potential for SK hynix to develop the world’s first-ever 12-layer HBM3.
4Mass Reflow Molded Underfill (MR-MUF): A course of through which semiconductor chips are stacked and a liquid protecting materials is injected into the area between the chips after which hardened to guard the chips and the encompassing circuitry. In comparison with making use of a film-type materials after every chip is stacked, MR-MUF is a extra environment friendly course of and affords efficient warmth dissipation.
5Self-alignment: The relocation of a die to its correct place by way of mass reflow throughout the MR-MUF course of. Warmth is utilized to the chips throughout this course of, inflicting the related bumps to soften and harden within the appropriate place.
As talked about above, wire, flip-chip, and TSV bonding serve their respective functions within the numerous areas of the packaging course of. Nonetheless, there’s a new interconnection method that has just lately emerged known as copper-to-copper direct bonding, which is a sort of hybrid bonding.
Hybrid bonding with chiplets
The time period “hybrid” is used to point that two sorts of interfacial bonding6 are being fashioned concurrently. The two sorts of interfacial bonding are: bonding between oxide interfaces and bonding between coppers. This expertise just isn’t a brand new improvement however has already been used within the mass manufacturing of CMOS picture sensors for a number of years. Nonetheless, it has attracted extra consideration just lately because of the elevated use of chiplets. Chiplet expertise separates particular person chips by operate after which reconnects them by way of packaging to implement quite a lot of capabilities on a single chip.
6Interfacial bonding: Bonding through which the surfaces of two our bodies in touch with each other are held collectively by intermolecular forces.
Though the performance of chiplets is a transparent good thing about the expertise, the first purpose for his or her adoption is cost-effectiveness. When all the capabilities are carried out on a single chip, the chip measurement will increase and inevitably results in losses in yield throughout wafer manufacturing. Moreover, whereas some areas of a chip could require costly and complicated expertise, different areas could be accomplished with cheaper legacy expertise. Thus, the fabrication course of turns into costly because the chip can’t be separated, so high-quality expertise is utilized to the entire chip even when solely a small space requires it. Nonetheless, the power of chiplet expertise to separate chip capabilities allows using both superior or legacy fabrication applied sciences and, thus, results in value financial savings.
Though the idea of chiplet expertise has been round for over a decade, it has not been extensively adopted because of the lack of improvement of packaging expertise that may interconnect chips. Nonetheless, latest advances in chip-to-wafer (C2W) hybrid bonding have considerably accelerated the adoption of chiplet expertise. C2W hybrid bonding affords a number of advantages. First, it permits solder-free bonding that reduces the thickness of the bonding layer, shortens {the electrical} path, and lowers resistance. Chiplets can, subsequently, function at excessive speeds with none compromise — simply as if it have been a single chip. Second, by bonding copper to copper instantly, pitches on the bumps could be dramatically lowered. At the moment, it’s troublesome to attain a bump pitch of 10 micrometers (μm) or much less when utilizing solder. Nonetheless, copper-to-copper direct bonding can scale back the pitch to lower than a μm, rising flexibility within the chip design. Third, it affords superior thermal dissipation, a function of packaging that can solely proceed to develop in significance sooner or later. Lastly, the skinny bonding layer and high-quality pitch talked about above impacts the shape issue of packaging, so the scale of the packaging could be dramatically lowered.
Nonetheless, like the opposite bonding applied sciences, hybrid bonding nonetheless has to beat challenges. To make sure strong high quality, particle management have to be improved on the nanometer scale, and controlling the flatness of the bonding layer stays a significant impediment. In the meantime, SK hynix plans to make use of essentially the most high-powered packaging resolution to develop hybrid bonding so it may be utilized to future HBM merchandise.
Advancing packaging tech with SK hynix’s hybrid bonding
Whereas SK hynix is at present growing hybrid bonding to use to its upcoming high-density, high-stack HBM product, the corporate has beforehand succeeded in stacking eight layers with hybrid bonding for HBM2E in 2022 whereas finishing electrical checks and guaranteeing primary reliability. This was a big feat as most circumstances of hybrid bonding to this point have been completed by way of single-layer bonding, or stacking with two chips face-to-face. For HBM2E, SK hynix efficiently stacked one base die and eight DRAM dies.
Hybrid bonding is essentially the most talked-about and highlighted bonding expertise within the packaging business. Built-in machine producers, foundries, and any firm able to producing superior packages are concentrating on hybrid bonding. As talked about above, the expertise nonetheless has a protracted strategy to go no matter its quite a few benefits. By its main HBM expertise, SK hynix will develop numerous packaging applied sciences along with hybrid bonding to assist packaging applied sciences and platform options attain unprecedented ranges.
